Etching Process Scalability and Challenges for ULK Materials - Archive ouverte HAL Access content directly
Conference Papers Year :

Etching Process Scalability and Challenges for ULK Materials

(1) , , (1, 2) , (3) , (3) , (3) , (1) , (1) , (1) , , , , , (1)


With the scaling down of integrated circuit devices, a constant effort is needed to improve the patterning technologies of interconnect stacks using either the metallic masking strategy or the organic masking strategy. Critical dimensions and profile control, plasma-induced damages (modifications, post etch residues, porous SiOCH roughening) are the key challenges to successfully pattern dual damascene porous SiOCH structures. We have compared the patterning performances of both masking strategies in terms of profile control. One of the main challenges is to optimize the plasma processes to minimize the dielectric sidewall modification. This has been achieved by using optimized or new characterization techniques such as scatterometric porosimetry, infrared spectroscopy, x-ray photoelectron spectroscopy.
Fichier principal
Vignette du fichier
chevolleau2010.pdf (1.14 Mo) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-00625314 , version 1 (17-10-2022)


Attribution - NonCommercial - CC BY 4.0



T. Chevolleau, N. Posseme, T. David, R. Bouyssou, J. Ducote, et al.. Etching Process Scalability and Challenges for ULK Materials. International Interconnect Technology Conference, IITC, Jun 2010, Dresde, Germany. ⟨10.1109/IITC.2010.5510735⟩. ⟨hal-00625314⟩
251 View
0 Download



Gmail Facebook Twitter LinkedIn More