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Article Dans Une Revue Materials Science Forum Année : 2009

Process Optimization for High Temperature SiC Lateral Devices

Résumé

Complementary lateral structures, N-JFETs. P-JFETS and bipolar diodes, have been implemented in p and n-type 4H-SiC wafers with epilayers. The device were optimized using finite element code MEDICI (TM) simulations, based oil ion implanted and etched Reduced-Surface-Field structures. Two Ti/Ni alloy composition are found to form ohmic contacts compatibles with high temperature device operation. 900 degrees C and respectively 1000 degrees C post-metallisation annealing during 2min are necessary. The presence of a graphite layer is determined by XPS (X-ray photon spectroscopy) analyses at the metal-semiconductor interface. Oil the fabricated p and n-type lateral JFETs in blocking state, breakdown voltage as high as 600V are obtained.
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hal-04368215 , version 1 (31-12-2023)

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Maher Soueidan, Mihai Lazar, Duy Minh Nguyen, Dominique Tournier, Christophe Raynaud, et al.. Process Optimization for High Temperature SiC Lateral Devices. Materials Science Forum, 2009, MATERIALS SCIENCE FORUM, 615-617, pp.585-588. ⟨10.4028/www.scientific.net/MSF.615-617.585⟩. ⟨hal-04368215⟩
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