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Conference Papers Year : 2023

Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design

Abstract

This work presents a comprehensive analysis of electrothermal effects in emerging 3D vertical junctionless nanowire transistors (VNWFETs) using on-wafer measurements under a wide range of temperature and validated against numerical and compact model simulations. Experimental observations indicate an increase of the drain current with the temperature, conforming to the behavior of junctionless FETs. Multiphysics simulations reveal formation of temperature hot-spots that adversely affect thermal conductivity in smaller geometries. The VNWFET compact model was then modified to account for the underlying electro-thermal effects as well as dynamic self-heating. Model simulations and the experimental results at different measurement temperatures for different transistor geometries show good agreement. The developed SPICE-compatible compact model was then used for studying the impact of electrothermal effects on the performances of basic 3D logic circuits.
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Friday, March 15, 2024
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Friday, March 15, 2024
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Dates and versions

hal-04231616 , version 1 (06-10-2023)

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Yifan Wang, Mukherjee Chhandak, Houssem Rezgui, Marina Deng, Cristell Maneux, et al.. Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design. IEEE 53rd European Solid-State Device Research Conference (ESSDERC 2023), Sep 2023, Lisbon, Portugal. pp.57-60, ⟨10.1109/ESSDERC59256.2023.10268560⟩. ⟨hal-04231616⟩
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