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Communication Dans Un Congrès Année : 2023

A RISC-V Instruction Set Extension for Flexible Hardware/Software Protection of Cryptosystems Masked at High Orders

Résumé

The paper presents an instruction set extension for the CV32E40P RISC-V processor core to protect cryptosystems against side channel attacks using masking at high orders. A first masking order is fixed in hardware at synthesis time. Then a higher masking order is obtained using software composition over the hardware one. The solution has been implemented, validated and evaluated in FPGA.
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Dates et versions

hal-04132900 , version 1 (19-06-2023)

Identifiants

  • HAL Id : hal-04132900 , version 1

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Fabrice Lozachmeur, Arnaud Tisserand. A RISC-V Instruction Set Extension for Flexible Hardware/Software Protection of Cryptosystems Masked at High Orders. 66th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2023) "Reinventing Microelectronics", Aug 2023, Phoenix, AZ, United States. ⟨hal-04132900⟩
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