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Conference Papers Year : 2022

Toward memory-centric scheduling for PREM task on multicore platforms, when processor assignments are specified

Abstract

Real-time embedded systems are increasingly being built using commercial-off-the-shelf (COTS) components. Although these components generally offer high performance, they can occasionally incur significant timing delays. Computing precise bounds on timing delays due to contention is difficult without a proper support from the hardware. Rather than estimating contention safe delays, this work aims to avoid it. We consider hardware architectures where each core has a scratchpad memory and the task execution is divided into a memory phase and a computation phase (Predictable Execution Model-PREM). Tasks are allocated to cores by a partitioned scheduling scheme. Then we schedule memory phases using a non-preemptive scheduling approach, while computation phases are scheduled using preemptive single core schedulers. This paper presents a new artificial deadline based approach to avoid contention in memory phases, where tasks memory phases are assigned appropriate deadlines and scheduled by a nonpreemptive scheduler (EDF). The effectiveness of the proposed method is evaluated using a set of synthetic experiments in terms of schedulability and analysis time.
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Dates and versions

hal-03938665 , version 1 (13-01-2023)

Identifiers

Cite

Ikram Senoussaoui, Mohammed Kamel Benhaoua, Houssam-Eddine Zahaf, Giuseppe Lipari. Toward memory-centric scheduling for PREM task on multicore platforms, when processor assignments are specified. EDiS 2022 - 3rd International Conference on Embedded & Distributed Systems, Nov 2022, Oran, France. pp.11-15, ⟨10.1109/EDiS57230.2022.9996534⟩. ⟨hal-03938665⟩
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