Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors - Archive ouverte HAL
Conference Papers Year : 2022

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors

Abstract

Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator.
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Dates and versions

hal-03765079 , version 1 (10-11-2022)

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Cite

Lucas Réveil, Mukherjee Chhandak, Cristell Maneux, Marina Deng, François Marc, et al.. Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2022), Oct 2022, Patras, Greece. 2 p., ⟨10.1109/VLSI-SoC54400.2022.9939576⟩. ⟨hal-03765079⟩
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