Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors
Résumé
Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator.
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