The role of a single defect on the electrical performance of transistors is unclear for transistors at nanometric dimensions. This role must be understood in order to improve the design and fabrication process of nanoscale transistors. Herein, we detected a single defect by a noise analysis approach on 18-nm-long gate junctionless (JL) vertical gate-all-around nanowire (VGAANW) transistors. Random telegraph signals (RTS) are reported to have a relative amplitude as high as 60%. We studied these RTS to assess the capacitive network in such nanoscale devices, providing routes to avoid large noise in the further downscaling of VGAANW and to exploit the high charge sensitivity for sensing applications. Defect density comparisons between JL and classic accumulation-mode transistors offered the opportunity to discuss a noise model developed when transistors were of several micrometers in size, questioning the significance of a defect density of less than one defect per device at the nanoscale.