Robustness of SiC MOSFET under avalanche conditions - Archive ouverte HAL Access content directly
Conference Papers Year : 2017

Robustness of SiC MOSFET under avalanche conditions


In high voltage direct current (HVDC) converters, a series connection of semiconductor devices is often used to achieve the desired blocking voltage. In such configuration, an unequal voltage sharing may drive one or more devices into avalanche breakdown, eventually causing the failure of the entire group of devices. This paper presents the experimental evaluation of SiC MOSFETs from different manufacturers operated in avalanche. A setup was developed to test the devices under such condition. The reliability of SiC MOSFETs have been compared. To correlate the experimental results with the failure mechanism, the MOSFETs were decapsulated to identify the failure sites on the SiC dies. Examination results show that for some tested devices, the failure occurs at the metallization source of the die, and results in a short circuit between all three terminals of the MOSFETs. Furthermore, it has been found that the parasitic BJT latch up and the intrinsic temperature limit are the main failure mechanisms for these devices.
Fichier principal
Vignette du fichier
papier_APEC_soumis.pdf (828.58 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-01535735 , version 1 (09-06-2017)



Ilyas Dchar, Marion Zolkos, Cyril Buttay, Hervé Morel. Robustness of SiC MOSFET under avalanche conditions. APEC, Mar 2017, Tampa, FL, United States. pp.2263-2268, ⟨10.1109/APEC.2017.7931015⟩. ⟨hal-01535735⟩
502 View
2082 Download



Gmail Facebook X LinkedIn More