For the first time, a structural physical modeling of the Intermediate-Layer-Dielectric (ILD) cracking in a planar-gate SiC MOSFET under short-pulse short-circuit is proposed. This new approach is based on Rankine's damage energetic description, relying on the SiO2 mechanical properties. Using a complete 2D high-temperature range electrothermal-metallurgical and elastoplastic-mechanical SiC MOSFET model, Rankine's sub-model is successfully implemented. The first results allow the extraction of crack penetration depth in a single pulse, prefiguring the average critical cycles number estimation to a possible complete destructive ILD fracture.