Towards simulation of an unified address space for 128-bit massively parallel computers - Archive ouverte HAL Accéder directement au contenu
Poster De Conférence Année : 2023

Towards simulation of an unified address space for 128-bit massively parallel computers

Résumé

High Performance Computing (HPC) supercomputers are composed of up to ten thousand nodes, each one having hundreds of cores organized around a shared memory. These nodes communicate through a high-performance communication network. Applications for HPC have increasing needs, both in terms of computational speed and the size of datasets to be processed. To follow these needs, memory in supercomputers is increasing at a rate such that, in the next decade, it will likely exceed 264 bytes. The RISC-V 128-bit ISA gives us the opportunity to rethink how memory is addressed and virtualized at the scale of a supercomputer. We are working on a platform to simulate a distributed 128-bit system with a global address space shared by the whole supercomputer.
Fichier principal
Vignette du fichier
2023-06-07-Eduardo-TOMASI-RIBEIRO-poster.pdf (306.02 Ko) Télécharger le fichier
2023-06-07-Eduardo-TOMASI-RIBEIRO-abstract.pdf (514.83 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)
Origine : Fichiers produits par l'(les) auteur(s)

Dates et versions

hal-04392810 , version 1 (14-01-2024)

Identifiants

  • HAL Id : hal-04392810 , version 1

Citer

Eduardo Tomasi, César Fuguet, Christian Fabre, Frédéric Pétrot. Towards simulation of an unified address space for 128-bit massively parallel computers. RISC-V Summit Europe 2023, Jun 2023, Barcelone, Spain. . ⟨hal-04392810⟩
22 Consultations
4 Téléchargements

Partager

Gmail Facebook X LinkedIn More