3D interconnects for III-V semiconductor heterostructures for miniaturized power devices
Résumé
Three-dimensional (3D) interconnects increase chip power density and enable miniaturization. Photonic chips require new processes to enable transitioning to 3D interconnects. We fabricate 3D interconnects on a multijunction solar cell, leveraging processes such as III-V heterostructure plasma etching, gold electrodeposition, and chemical-mechanical polishing to integrate through substrate vias to the heterostructure. Wafer bonding is used to handle 20-μm-thin III-V films. The strategy enables us to demonstrate photonic power devices having areas 3 orders of magnitude smaller compared to standard chips. The design also yields a small shading factor below 3%. Compared to miniaturized photonic power devices with two-dimensional connections, 3D interconnects achieve a 6-fold increase in wafer area use. These improvements will enhance the power yield per wafer while unlocking high-density and miniaturized devices for applications such as power over fiber, the internet of things, and microconcentrator photovoltaics.
Domaines
Sciences de l'ingénieur [physics]| Origine | Publication financée par une institution |
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