Nanoscale Thermal Transport in Vertical Gate-All-Around Junctionless Nanowire Transistors—Part I: Experimental Methods
Résumé
In this paper, we present the first detailed experimental study of electro-thermal effects in 3D vertical gate-all-around junctionless nanowire transistors (JLNT). In contrast with conventional CMOS technologies, JLNTs exhibit steady increase of current with temperature owing to weak mobility degradation in the highly doped nanowires. Consequently, in this work, we proposed novel experimental methods for extracting thermal resistance using DC and low-frequency S-parameter measurements. Experimental results obtained from different methods are validated against theoretical as well as simulated values obtained from multiphysics simulation of JLNTs.
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