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Communication Dans Un Congrès Année : 2023

Evidence of Trapping and Electrothermal Effects in Vertical Junctionless Nanowire Transistors

Résumé

Understanding trap dynamics and formation of localized temperature hot-spots due to self-heating is crucial for the design optimization of emerging vertical junctionless nanowire transistors (VNWFET). This works investigates the operation of an 18nm VNWFET technology for the first time leveraging pulsed current-voltage measurements. Results indicate increased trap activity as well as electrothermal effects with increasing pulse width. Multiphysics simulations are then used to provide a deeper insight into the nanoscale transport of the VNWFETs.
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Dates et versions

hal-04231605 , version 1 (06-10-2023)

Identifiants

  • HAL Id : hal-04231605 , version 1

Citer

Yifang Wang, Houssem Rezgui, Mukherjee Chhandak, Marina Deng, Abhishek Kumar, et al.. Evidence of Trapping and Electrothermal Effects in Vertical Junctionless Nanowire Transistors. 9th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS) 2023, May 2023, Tarragona, Spain. ⟨hal-04231605⟩
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