Achieving high decoding throughput and latency has been challenging for turbo decoders due to the limitations in terms of parallelism on component decoder level. To alleviate this issue, we propose an iteration overlap scheme able to apply a decoding schedule tailored to both, the decoder hardware architecture and the interleaver constraints. The proposal aims to minimize the achieved decoding latency without penalizing performance when compared to baseline decoders. To that end, we formulate the window schedule optimization problem when applying iteration overlap in pipelined Turbo Decoder hardware architectures. Then, we propose a method to find optimal window schedules under realistic assumptions. Results demonstrate that latency is reduced by 20 − 25% for most Long Term Evolution (LTE) interleaver configurations. For specific interleavers, the achieved latency reduction can be as high as 62%. This indicates that further latency savings could be achieved if iteration overlap is taken into account when designing interleavers.