A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology - Archive ouverte HAL
Article Dans Une Revue IEEE Transactions on Circuits and Systems II: Express Briefs Année : 2023

A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

Résumé

This brief presents the design of a dual-loop PLL for indoor and outdoor positioning. The proposed architecture is a dual-mode frequency synthesizer. It allows addressing either GNSS or WiFi. Thus, WiFi can assist GNSS for indoor positioning, while GNSS takes care of outdoor positioning. It achieves a high bandwidth with fine resolution without using the fractional-N approach. The PLL operates for the WiFi mode with 57 channels from 5.16 GHz to 5.72 GHz with a 10 MHz channel spacing and for the GNSS mode at frequency bands of GPS, Galileo, GLONASS, Beidou, and IRNSS. The Phase Noise of the designed PLL at 1 MHz offset from the carrier is –97.37 dBc/Hz and –104.58 dBc/Hz for WiFi and GNSS, respectively, and the power consumption is 1.127 mW and 0.749 mW. The total active area is 0.346mm2 . This architecture is the first of its kind for both indoor positioning and outdoor positioning.
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Dates et versions

hal-04166890 , version 1 (22-05-2024)

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Mateus B. Moreira, Francois Rivet, Magali de Matos, Herve Lapuyade, Yann Deval. A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, pp.1-5. ⟨10.1109/tcsii.2023.3292428⟩. ⟨hal-04166890⟩
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