A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue IEEE Transactions on Circuits and Systems II: Express Briefs Année : 2023

A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology

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hal-04166890 , version 1 (20-07-2023)

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Mateus B. Moreira, Francois Rivet, Magali de Matos, Herve Lapuyade, Yann Deval. A (0.75-1.13)mW and (2.4-5.2)ps RMS jitter Integer-N based Dual-Loop PLL for Indoor and Outdoor Positioning in 28nm FD-SOI CMOS Technology. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, pp.1-1. ⟨10.1109/tcsii.2023.3292428⟩. ⟨hal-04166890⟩
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