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Article Dans Une Revue Microelectronics Reliability Année : 2022

AC stress analysis of trench-based multi-gate transistors in a 40 nm e-NVM technology

Résumé

This work addresses the reliability of different architectures of novel high-density multi-gate transistors manufactured in a 40 nm embedded Non-Volatile Memory process technology. The multi-gate architectures are based on lateral transistors integrated in deep trenches built alongside the main planar transistor. These architectures increase the conduction channel width with a weak impact on the footprint. A reliability study based on AC stress tests is carried out to monitor the multi-gate oxide degradation and in particular the interaction between planar and vertical oxides is highlighted. Finally, a benchmark of stress immunity, among the three studied multi-gate architectures, is presented.
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Dates et versions

hal-04063483 , version 1 (09-04-2023)

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R. Gay, V. Della Marca, H. Aziza, P. Chiquet, A. Regnier, et al.. AC stress analysis of trench-based multi-gate transistors in a 40 nm e-NVM technology. Microelectronics Reliability, 2022, 138, pp.114732. ⟨10.1016/j.microrel.2022.114732⟩. ⟨hal-04063483⟩
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