For very high-speed satellite communication (up to 10 Gbit/s), the natural level of parallelism of a single decoder might be insufficient to achieve the decoding throughput. A known solution is to implement several decoder cores working in parallel. This solution entails efficient control and design of the input and output buffers to regulate the varying number of decoding iterations of each decoder. This paper presents a methodology to build such a system effectively for iterative decoders with stopping criteria. As an application, we present the result of the implementation of 3 DVB-S2/S2X decoders in a single FPGA. Simulation results of the whole system show performance within (or very close to) the standard requirements. The implementation can handle code rates from 13/45 (3.3 Gbit/s air throughput) up to 9/10 (10 Gbit/s air throughput) for several modulation sizes.