C2QoS: Network QoS guarantee in vSwitch through CPU-cycle management - Archive ouverte HAL
Journal Articles Journal of Systems Architecture Year : 2021

C2QoS: Network QoS guarantee in vSwitch through CPU-cycle management

Ye Yang
Haiyang Jiang
  • Function : Author
Yulei Wu
Chunjing Han
  • Function : Author
Yilong Lv
  • Function : Author
Xing Li
  • Function : Author
Bowen Yang
  • Function : Author
Serge Fdida
Gaogang Xie
  • Function : Author

Abstract

Cyber–Physical–Social–System (CPSS) relies on cloud and edge computing for service deployment and acceleration. As an enabling technology of CPSS, network virtualization allows different services to be deployed on a single physical server and provides them with differentiated network performance based on service-level-agreement (SLA). Unfortunately, current virtual switches (vSwitches) cannot guarantee this functionality due to the common resource competition and unpredictable processing capacity. As a software process on the server, vSwitch is allocated limited dedicated CPU cores to implement traffic forwarding for all services. But the QoS strategy inheriting from the hardware switch, does not consider the forwarding tasks’ competition for CPU cores in terms of utilization and timing, thus cannot guarantee the SLA. To solve this critical issue, we propose a CPU-cycle based QoS (C2QoS) strategy to realize the isolation and guarantee of service network performance by managing the usage and scheduling of the IO-dedicated CPU cores in vSwitch. C2QoS includes a CPU-cycle based token bucket mechanism to strictly limit service’s network bandwidth and a hierarchical batch scheduling mechanism to achieve hierarchical latency. Experimental results show that, compared with existing strategies, C2QoS can strictly guarantee the network bandwidth of the services and reduce the service latency by up to 80%.
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Dates and versions

hal-04004818 , version 1 (24-05-2023)

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Ye Yang, Haiyang Jiang, Yulei Wu, Chunjing Han, Yilong Lv, et al.. C2QoS: Network QoS guarantee in vSwitch through CPU-cycle management. Journal of Systems Architecture, 2021, 116, pp.102148. ⟨10.1016/j.sysarc.2021.102148⟩. ⟨hal-04004818⟩
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