New emerging Vertical NanoWire Field-E昀昀ect Transistors (VNWFET) appear promising for compact energy e昀케cient computing architectures, still, we notice a lack of technology aware and coherent design methodologies. Such tools would enable a thorough exploration of the bene昀椀ts of these new technologies at the circuit level. This paper explores a complete methodology for designing a logic cell library using VNWFET. The methodology includes low-level logic cells Technology Computer Aided Design (TCAD) simulations, Parasitic Extraction (PEX) of predictive devices and 3D physical design rules and cell generation. In this design method, we focus on the standard CMOS logic cells, with up to 12 transistors and detail the inter-transistor routing. The various cells generated using this method are tested using TCAD and selected based on their PEX results. The whole process is performed on logic cell examples and in the light of the current design context, results show an improvement in footprint area optimization.