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Article Dans Une Revue IEEE Letters on Electromagnetic Compatibility Practice and Applications Année : 2022

A Comparative Performance Analysis of 6T & 9T SRAM Integrated Circuits: SOI vs. Bulk

Résumé

This paper evaluates the performance of 6T & 9T static random access memory (SRAM) cells, for data stability and power metrics, with the aim to compare silicon-on-insulator (SOI) and bulk CMOS technologies. Each SRAM topology was designed & simulated in 180 nm 5 V XFAB-SOI and AMS-bulk processes, using optimized parameters and compatible devices. The fundamental variables analyzed were read noise margins, write trip current & voltage as well as leakage current (LC) and static power dissipation (SPD) under process and temperature (PT) variations. The static noise margin (SNM) butterfly curve and N-curve methodologies were used to assess the mentioned parameters. Compared to bulk technology, the SRAM cells designed with SOI were found to have lower SPD & LC, higher data stability, lower write ability, larger sensitivity to process variations and higher resilience to temperature deviations.
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Dates et versions

hal-03629861 , version 1 (29-11-2023)

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Qazi Mashaal Khan, Richard Perdriau, Mohamed Ramdani, Mohsen Koohestani. A Comparative Performance Analysis of 6T & 9T SRAM Integrated Circuits: SOI vs. Bulk. IEEE Letters on Electromagnetic Compatibility Practice and Applications, 2022, 4 (2), pp.25-30. ⟨10.1109/LEMCPA.2022.3163963⟩. ⟨hal-03629861⟩
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