Harmonic communication is an option for enhancing tag to reader communication in UHF RFID systems. In this work different voltage multiplier configurations, diodes, operation scenarios and generated harmonics have been evaluated at simulation level in order to suggest voltage multiplier design guides to increase the available harmonic power. The results show that single side topologies with minimum amount of stages are preferred. Regarding the diode, a proposed modified PMOS diode has shown higher generated harmonic power than Schottky diodes. Regarding the generated harmonics, the second order harmonic is more sensitive to the design parameters. It can be generated with a maximum power of −30 dBm for an input power of −20 dBm. In the case of the third order harmonic, the obtained power is more stable against the design variations and has a maximum value of −34 dBm.