This paper introduces an extension of Timed Petri Nets for the modeling of synchronous electronic circuits, addressing pipeline design problems. Petri Nets have been widely used for the modeling of electronic circuits. In particular, Timed Petri Nets which capture timing properties are perfectly suited for scheduling problems. Our extension, through reset that model the pipeline stages, and through delayable transitions that relax timing constraints, allows to widen the conception space of pipelined systems. After discussing maximal-step firing rule and the semantics of Timed Petri Nets "à la Ramchandani", we define our Timed Petri Nets with reset and delayable (non-asap) transitions. We then study the decidability and the complexity of the main problems of interest. We propose an abstraction of the state space. We then establish a translation of this model into a single-clock timed automata, which preserves the language. This translation settles the decidability on language inclusion and universality problems. Finally, an algorithm for the exploration of the state space is provided, and can be driven by the optimisation of various properties of the pipeline.