Single-Event Latchup (SEL) is considered as a major reliability issue for the CMOS technology due to its capability of permanently damaging electronic components. In this work, the impact of temperature variation on the SEL mechanism is investigated. As the SEL sensitivity is influenced by design and environment parameters, the temperature variation is also evaluated along the variation of three parameters related to the geometry and to the design of the component: the doping profile, the anode to cathode spacing (A-C spacing) and the substrate and well taps placement. Moreover, the charge collection process has been analyzed. The goal was to verify whether the concept of critical charge, through studying the collected charge by the source implants, can be used for SEL, as it is used for upsets. 2D TCAD simulations have been performed, using an NPNP structure based on 65nm CMOS inverter. From these simulations, we have analyzed the threshold LET and SEL rate. Results show that temperature impact is stronger when the component is less sensitive to SEL. Moreover, charge collected has shown promising results about its usage for SEL.