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Article Dans Une Revue IET Microwaves Antennas and Propagation Année : 2019

About 250/285 GHz push–push oscillator using differential gate equalisation in digital 65‐nm CMOS

Résumé

This study presents a push-push oscillator architecture based on differential gate equalisation to enhance theoscillation frequency while providing relatively high output power with ultra-compact layout form factor. The frequencyenhancement is derived as a function of the equivalent RLC model of the oscillator's main constituents. The proposed principleis applied to a terahertz oscillator in the 200-300 GHz range to mitigate the excessive substrate and skin effect losses instandard digital 65-nm complementary metal-oxide-semiconductor technology at such high frequencies. The design concept isvalidated using two single-stage push-push oscillators. The first oscillator shows -8.1 dBm output power at 250 GHz oscillationfrequency and -106.8 dBc/Hz phase noise at 10 MHz offset while consuming 76 mW power from 1.5 V DC supply voltage. Thechip area is 200 × 250 μm2. The second oscillator provides -14.8 dBm output power at 285 GHz and -106 dBc/Hz phase noiseat 10 MHz offset with 80 mW power consumption from 1.5 V DC supply. The chip area is 200 × 200 μm2.
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Dates et versions

hal-03133845 , version 1 (09-06-2022)

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Bassem Fahs, Kefei Wu, Walid Aouimeur, Muhammad Waleed Mansha, Christophe Gaquière, et al.. About 250/285 GHz push–push oscillator using differential gate equalisation in digital 65‐nm CMOS. IET Microwaves Antennas and Propagation, 2019, 13 (12), pp.2073-2080. ⟨10.1049/iet-map.2018.5308⟩. ⟨hal-03133845⟩
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