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Communication Dans Un Congrès Année : 2018

Reducing AFDX jitter in a mixed NoC/AFDX architecture

Résumé

Current avionics architecture are based on an avionics full duplex switched Ethernet network (AFDX) that interconnects end systems. Avionics functions exchange data through Virtual Links (VLs), which are static flows with bounded bandwidth. The jitter for each VL at AFDX entrance has to be less than 500 ps. This constraint is met, thanks to end system scheduling. The interconnection of many-cores by an AFDX backbone is envisionned for future avionics architecture. The principle is to distribute avionics functions on these many-cores. Many-cores are based on simple cores interconnected by a Network-on-Chip (NoC). The allocation of functions on the available cores as well as the transmission of flows on the NoC has to be performed in such a way that the jitter for each VL at AFDX entrance is still less than 500 μs. A first solution has been proposed, where each function manages the transmission of its VLs. The idea of this solution is to distribute functions on each many-core in order to minimize contentions for VLs which concern functions allocated on different many-cores. In this paper, we consider that VL transmissions are managed by a single task in each many-core. We show on a preliminary case study that this solution significantly reduces VL jitter.
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Dates et versions

hal-03044230 , version 1 (11-12-2020)

Identifiants

Citer

Laure Abdallah, Jérôme Ermont, Jean-Luc Scharbarg, Christian Fraboul. Reducing AFDX jitter in a mixed NoC/AFDX architecture. IEEE 14th International Workshop on Factory Communication Systems (WFCS 2018), Jun 2018, Imperia, Italy. pp.1--4, ⟨10.1109/WFCS.2018.8402375⟩. ⟨hal-03044230⟩
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