From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technology
Résumé
The emergence of new hardware-oriented algorithms for convolutional neural networks (CNNs) or spiking neural networks (SNNs) used for efficient data interpretation, made neuromorphic computing a very promising solution. SNNs are very attractive due to their particularly low power consumption. This paper presents a comprehensive analysis of an analog spiking neuron designed in 28 nm UTBB FD-SOI CMOS technology from STMicroelectronics. Thick oxide MOS transistors with regular VT are selected to perform a low power design enhanced by using sub-threshold bias. The neuron operation is presented and analyzed through SPICE simulations performed at 0.7 V nominal voltage bias. Several parameters control the shape of the neuron response, such as: the synaptic excitation, the spike duration, and the refractory period. The neuron under study was fabricated and characterized for bias voltages ranging from 1.8 V standard bias to the measured limit of 0.19 V. The full functionality of the analog spiking neuron in FD-SOI is demonstrated.
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