For CMOS processing compatibility, hybrid bonding of III-V materials on Silicon should be operated below 300°C, requiring an interfacial layer as thin as possible in order not to hamper the electrical transport through the interface. Both SiO 2 and ZnO interfacial layers have been investigated in the case of n-InP/n-Si hybrid heterostructures. Efficient electrical transport through oxide-mediated bonded InP/Si heterostructures is demonstrated, related to tunneling through the oxide-interfacial layer. These electrically-operated oxide-interfacial-layer heterostructures provide both efficient bonding processing and open the field for full 3D design and operation of optoelectronic devices.