Influence of different peripheral protections on the breakover voltage of a 4H-SiC GTO thyristor
Résumé
4H-SiC asymmetrical gate turn-off (GTO) thyristors have been developed using a PP-NP+ epitaxial layer structure, where P is a 35 µm thick p-type drift layer doped at 5E14 cm-3. The process sequence, described in details elsewhere, uses plasma etching steps (ECR and RIE) in order to expose interdigitated devices with a recessed gate structure. Knowing the difficulty in reaching the theoretical forward blocking capability of Vb = 6 kV, determined by numerical simulations using the finite element code MEDICITM, three different device terminations are realized. The first and simplest termination used is a MESA etched down to 12 µm deep into the drift layer. Better performance was expected by using a combination of MESA and Junction Termination Extension (JTE), but unfortunately, the JTE implantation was not well adjusted. Finally, etched guard ring (EGR) terminations are realized etching five 2 µm wide grooves around the device periphery through the n-base layer. The electric characteristics of the devices with all the three terminations are presented and discussed using the results of numerical simulations. The highest breakover voltage measured amounts to 4.0 kV, approaching the theoretical limit of 0.63·Vb, calculated for plane parallel junction.
Domaines
Energie électriqueOrigine | Fichiers produits par l'(les) auteur(s) |
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