Communication Dans Un Congrès Année : 2006

Formal and efficient verification techniques for Real-Time UML models

Résumé

The real-time UML profile TURTLE has a formal semantics expressed by translation into a timed process algebra: RT-LOTOS. RTL, the formal verification tool developed for RT-LOTOS, was first used to check TURTLE models against design errors. This paper opens new avenues for TURTLE model verification. It shows how recent work on translating RT-LOTOS specifications into Time Petri net model may be applied to TURTLE. RT-LOTOS to TPN translation patterns are presented. Their formal proof is the subject of another paper. These patterns have been implemented in a RT-LOTOS to TPN translator which has been interfaced with TINA, a Time Petri Net Analyzer which implements several reachability analysis procedures depending on the class of property to be verified. The paper illustrates the benefits of the TURTLE RT-LOTOS TPN transformation chain on an avionic case study.

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hal-02270428 , version 1 (25-08-2019)

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  • HAL Id : hal-02270428 , version 1

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T Sadani, P de Saqui-Sannes, J.-P Courtiat. Formal and efficient verification techniques for Real-Time UML models. Conference ERTS'06, Jan 2006, Toulouse, France. ⟨hal-02270428⟩
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