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            <title xml:lang="en">Formal and efficient verification techniques for Real-Time UML models</title>
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            <idno type="stamp" n="UNIV-TLSE2">Université Toulouse 2</idno>
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            <idno type="stamp" n="LAAS">Laboratoire d'analyse et d'architecture des systèmes</idno>
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                <title xml:lang="en">Formal and efficient verification techniques for Real-Time UML models</title>
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              <p>The real-time UML profile TURTLE has a formal semantics expressed by translation into a timed process algebra: RT-LOTOS. RTL, the formal verification tool developed for RT-LOTOS, was first used to check TURTLE models against design errors. This paper opens new avenues for TURTLE model verification. It shows how recent work on translating RT-LOTOS specifications into Time Petri net model may be applied to TURTLE. RT-LOTOS to TPN translation patterns are presented. Their formal proof is the subject of another paper. These patterns have been implemented in a RT-LOTOS to TPN translator which has been interfaced with TINA, a Time Petri Net Analyzer which implements several reachability analysis procedures depending on the class of property to be verified. The paper illustrates the benefits of the TURTLE RT-LOTOS TPN transformation chain on an avionic case study.</p>
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