Certified and efficient instruction scheduling. Application to interlocked VLIW processors.
Résumé
CompCert is a moderately optimizing C compiler with a formal, machine-checked, proof of correctness: after successful compilation, the assembly code has a behavior faithful to the source code. Previously, it only supported target instruction sets with sequential semantics, and did not attempt reordering instructions for optimization.
We present here a CompCert backend for a VLIW core (i.e. with explicit parallelism at the instruction level), the first CompCert backend providing scalable and efficient instruction scheduling. Furthermore, its highly modular implementation can be easily adapted to other VLIW or non-VLIW pipelined processors.
Mots clés
CCS Concepts: • Software and its engineering → Formal software verification
Retargetable com- pilers
• Theory of computation → Scheduling algorithms
• General and reference → Performance
• Computer systems organization → Superscalar architectures
Very long instruction word Additional Key Words and Phrases: Formal verification of compiler optimizations
Instruction-level parallelism
the Coq proof assistant
Symbolic execution
Hash-consing
Origine | Fichiers produits par l'(les) auteur(s) |
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