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Journal Articles IEEE Embedded Systems Letters Year : 2019

Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators

Abstract

Domain-specific acceleration is now a "must" for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the design productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow models of computation with Coarse-Grained Reconfigurable (CGR) architectures can be particularly handful. In this paper we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on dataflow and functional programming principles, capable of addressing design productivity issues for CGR accelerators. The main advantage of the proposed methodology is accurate IP-level latency predictability improving Design Space Exploration (DSE) when compared to state-of-the-art High-Level Synthesis (HLS).
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Dates and versions

hal-02062002 , version 1 (08-03-2019)

Identifiers

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Claudio Rubattu, Francesca Palumbo, Carlo Sau, Rubén Salvador, Jocelyn Sérot, et al.. Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators. IEEE Embedded Systems Letters, 2019, 11 (3), pp.69-72. ⟨10.1109/LES.2018.2882989⟩. ⟨hal-02062002⟩
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