Analysis and modelling of wafer level process variability in advanced FD-SOI devices using split C-V and gate current data - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2018

Analysis and modelling of wafer level process variability in advanced FD-SOI devices using split C-V and gate current data

Fichier non déposé

Dates et versions

hal-02051931 , version 1 (28-02-2019)

Identifiants

  • HAL Id : hal-02051931 , version 1

Citer

Krishna Pradeep, Theano Karatsori, Thierry Poiroux, Andre Juge, Patrick Scheer, et al.. Analysis and modelling of wafer level process variability in advanced FD-SOI devices using split C-V and gate current data. Modeling of Systems and Parameter Extraction Working (MOS-AK), ESSDERC/ESSCIRC, Sep 2018, Dresden, Germany. ⟨hal-02051931⟩
18 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More