Many application-specific processor design approaches are being proposed and investigated nowadays. All of them aim to cope with the emerging flexibility requirement combined with the best performance efficiency. Application Specific Instruction-set Processor (ASIP) design approach is among the most explored, and thus in many application domains. However, this concept implies a dynamic scheduling of a set of instructions which generally lead to an overhead related to instruction decoding. To reduce this overhead, other approaches were proposed using static scheduling of datapath control signals. This paper presents a design of a custom architecture for a Minimum Mean Square Error Interference Cancellation (MMSE-IC) Linear Equalizer (LE) used in iterative MIMO turbo receiver using NO Instruction Set Computer (NISC) design approach. The proposed processor has a datapath, memory, and a simple controller with no instruction set or instruction decoder. NISC compiler schedules statically all operations and generates control values that must be driven to datapath components at every clock cycle and loads them in the memory. At runtime the controller only loads the control words and applies them to the datapath.