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Communication Dans Un Congrès Année : 2006

Semi-Iterative Analog Turbo Decoding

Matthieu Arzel
Fabrice Seguin
Cyril Lahuec
Michel Jezequel

Résumé

This paper presents a novel analog turbo decoding architecture allowing analog decoders for long frame lengths to be implemented on a single chip. This is made possible by suitably using slicing techniques which allow hardware reuse and re-configurability. The architecture is applied to a DVB-RCS-like CRSC code. It shows a reduction of occupied chip area by a factor of ten when compared to a conventional slice design with no significant performance degradation. A single 27mm2 0.25gm BiCMOS decoder can then decode any frame length from 40 up to 1824 bits.
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Dates et versions

hal-01809339 , version 1 (06-06-2018)

Identifiants

  • HAL Id : hal-01809339 , version 1

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Matthieu Arzel, Fabrice Seguin, Cyril Lahuec, Michel Jezequel. Semi-Iterative Analog Turbo Decoding. ISCAS 2006 : International Symposium on Circuits and Systems, Kos, Greece, May 21-24, May 2006, Kos, Greece. pp.3562 - 3565. ⟨hal-01809339⟩
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