Semi-Iterative Analog Turbo Decoding
Résumé
This paper presents a novel analog turbo decoding architecture allowing analog decoders for long frame lengths to be implemented on a single chip. This is made possible by suitably using slicing techniques which allow hardware reuse and re-configurability. The architecture is applied to a DVB-RCS-like CRSC code. It shows a reduction of occupied chip area by a factor of ten when compared to a conventional slice design with no significant performance degradation. A single 27mm2 0.25gm BiCMOS decoder can then decode any frame length from 40 up to 1824 bits.
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