On the one hand, a strength of FPGAs is their ability to perform non-standard computations not supported by classical microprocessors. Many libraries of highly customizable application-specific IPs have been developed to exploit this strength. On the other hand, HLS tools, which allow to program an FPGA using a dialect of the C language, are gaining traction. However, the ease of use of the C language becomes a hindrance when one wants to express non-standard computations. Indeed, the C language was designed for programming microprocessors and carries with it many restrictions of the microprocessor paradigm. This is especially true when computing with floating-point, whose data-types and evaluation semantics are defined by the IEEE-754 and C11 standards. If the high-level specification was a computation on the reals, HLS imposes a very restricted implementation space. This work attempts to bridge FPGA application-specific efficiency and HLS ease of use. This is illustrated on the ubiquitous floating-point summation-reduction pattern. A source-to-source compiler rewrites, inside critical loop nests of the input C code, selected floating-point additions into sequences of simpler operators using non-standard arithmetic formats. Evaluation of this method demonstrates that the benefits of application-specific operators (better performance and better accuracy) can be brought to HLS workflows while keeping their ease of use.