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Conference Papers Year : 2016

Autonomic Parallelism and Thread Mapping Control on Software Transactional Memory

Abstract

Parallel programs need to manage the trade-offbetween the time spent in synchronization and computation.The time trade-off is affected by the number of active threadssignificantly. High parallelism may decrease computing time whileincrease synchronization cost. Furthermore thread locality ondifferent cores may impact on program performance too, asthe memory access time can vary from one core to anotherdue to the complexity of the underlying memory architecture.Therefore the performance of a program can be improved byadjusting the number of active threads as well as the mapping ofits threads to physical cores. However, there is no universal rule todecide the parallelism and the thread locality for a program froman offline view. Furthermore, an offline tuning is error-prone.In this paper, we dynamically manage parallelism and threadlocalities. We address multiple threads problems via SoftwareTransactional Memory (STM). STM has emerged as a promisingtechnique, which bypasses locks, to address synchronization issuesthrough transactions. Autonomic computing offers designers aframework of methods and techniques to build autonomic systemswith well-mastered behaviours. Its key idea is to implementfeedback control loops to design safe, efficient and predictablecontrollers, which enable monitoring and adjusting controlledsystems dynamically while keeping overhead low. We propose todesign a feedback control loop to automate thread managementat runtime and diminish program execution time.
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Dates and versions

hal-01309681 , version 1 (26-07-2016)

Identifiers

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Naweiluo Zhou, Gwenaël Delaval, Bogdan Robu, Eric Rutten, Jean-François Méhaut. Autonomic Parallelism and Thread Mapping Control on Software Transactional Memory. ICAC 2016 - 13th IEEE International Conference on Autonomic Computing, Jul 2016, Wurzburg, Germany. pp.189 - 198, ⟨10.1109/ICAC.2016.54⟩. ⟨hal-01309681⟩
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