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Article Dans Une Revue IEEE Transactions on Circuits and Systems II: Express Briefs Année : 2017

A Novel Architecture For Elementary Check Node Processing In Non-Binary LDPC Decoders

Ali Al Ghouwayel
Emmanuel Boutillon

Résumé

This paper presents an efficient architecture design for Elementary Check Node processing in Non-Binary Low-Density Parity-Check decoders based on the Extended Min-Sum algorithm. This architecture relies on a simplified version of the Bubble Check algorithm and is implemented by the means of FIFOs. The adoption of this new design at the Check Node level results in a high-rate low-cost full-pipelined processor. A proof-of-concept implementation of this processor shows that the proposed architecture halves the occupied FPGA surface and doubles the maximum frequency without modifying the input/output behavior of the previous one.

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Electronique
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hal-01298785 , version 1 (06-04-2016)

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Oussama Abassi, Laura Conde-Canencia, Ali Al Ghouwayel, Emmanuel Boutillon. A Novel Architecture For Elementary Check Node Processing In Non-Binary LDPC Decoders. IEEE Transactions on Circuits and Systems II: Express Briefs, 2017, 64 (2), pp.136-140. ⟨10.1109/TCSII.2016.2551550⟩. ⟨hal-01298785⟩
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