Full-Speed Deterministic Bit-Accurate Parallel Floating-Point Summation on Multi- and Many-Core Architectures - Archive ouverte HAL Accéder directement au contenu
Rapport Année : 2014

Full-Speed Deterministic Bit-Accurate Parallel Floating-Point Summation on Multi- and Many-Core Architectures

Résumé

On modern multi-core, many-core, and heterogeneous architectures, floating-point computations, especially reductions, may become non-deterministic and thus non-reproducible mainly due to non-associativity of floating-point operations. We introduce a solution to compute eterministic sums of floating-point numbers efficiently and with the best possible accuracy. Our multi-level algorithm consists of two main stages: a filtering stage that uses fast vectorized floating-point expansions; an accumulation stage based on superaccumulators in a high-radix carry-save representation. We present implementations on recent Intel desktop and server processors, on Intel Xeon Phi accelerator, and on AMD and NVIDIA GPUs. We show that the numerical reproducibility and bit-perfect accuracy can be achieved at no additional cost for large sums that have dynamic ranges of up to 90 orders of magnitude by leveraging arithmetic units that are left underused by standard reduction algorithms.
Fichier principal
Vignette du fichier
superaccumulator.pdf (244.14 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)

Dates et versions

hal-00949355 , version 1 (25-02-2014)
hal-00949355 , version 2 (28-02-2014)
hal-00949355 , version 3 (09-02-2015)
hal-00949355 , version 4 (10-09-2015)

Identifiants

  • HAL Id : hal-00949355 , version 1

Citer

Caroline Collange, David Defour, Stef Graillat, Roman Iakymchuk. Full-Speed Deterministic Bit-Accurate Parallel Floating-Point Summation on Multi- and Many-Core Architectures. 2014. ⟨hal-00949355v1⟩
2328 Consultations
3469 Téléchargements

Partager

Gmail Facebook X LinkedIn More