Compression of redundancy free trellis stages in Turbo-Decoder - Archive ouverte HAL
Article Dans Une Revue Electronics Letters Année : 2013

Compression of redundancy free trellis stages in Turbo-Decoder

Résumé

For turbo code with coding rate close to one, the high puncturing rate induces long sequences of trellis without redundancy bit. A simplification technique to compute the final state of a sequence of Redundancy Free Trellis Stage (RFTS) is presented. It compresses a sequence of RFTS of length $N$ into a sequence of RFTS of length $m-1 + (N \mod (m-1))$, where $m$ is the number of states of the trellis. The computation is reduced accordingly.
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Dates et versions

hal-00825275 , version 1 (23-05-2013)

Identifiants

  • HAL Id : hal-00825275 , version 1

Citer

Emmanuel Boutillon, José-Luis Sanchez-Rojas, Cédric Marchand. Compression of redundancy free trellis stages in Turbo-Decoder. Electronics Letters, 2013, 49 (7), pp.460 - 462. ⟨hal-00825275⟩
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