Systems mapped on CMOS architectures are often expected to achieve high processing bandwidth and low energy consumption. However, a specific care should be paid to adequate the algorithm structure to the circuit architecture when designing multimedia wireless embedded networking systems. This paper addresses the problem of low power consumption and real time constraints for image communication in wireless camera sensor networks (WCSN). It presents a low-complexity hardware implementation of JPEG-like encoder for image compression and paquetization. The designed circuit is planned to be embedded in the camera sensor node to relieve the main processor of the data processing tasks. This encoder combines the best lifting DCT algorithm of the literature with a zonal coding approach. The former reduces the number of operations required per DCT coefficient while the latter reduces the number of coefficients to be computed, quantized and encoded. We study the tradeoff between the size of the zonal mask (a square zone of size k) and the visual image quality as a function of the compression bitrate, then we describe the hardware features of the JPEG-like circuit when implemented on different FPGAs and ASIC prototypes. Performance evaluation is provided for several ranges of compression bitrate, accordingly with the right value of k. Considering a grayscale image compressed to 0.25 bpp for example, k=4 is the best choice. In this case, and for an image of 128×128 pixels, the CMOS circuit of the proposed encoder, synthesized using 45 nm integration technology, clocks at 360 MHz and consumes 18.02 mW. It outperforms most of similar circuits being presented in the literature.