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Conference Papers Year : 2008

A 2GHz 65nm CMOS digitally-tuned BAW oscillator

Abstract

The design of a 2GHz reference frequency oscillator in a 65nm CMOS process using a Bulk Acoustic Wave resonator is presented. The oscillator implements digital frequency control using a switched capacitor bank in parallel to the resonator. The tuning range is up to 4MHz with a minimum step of 1.6kHz. The oscillator core is designed to reach low phase noise (-128dBc/Hz at 100kHz offset) at low power consumption (0.9mW) using a differential topology. It is followed by a low noise divider for output at 500MHz with a phase noise of -140dBc/Hz at 100kHz offset.
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Dates and versions

hal-00621923 , version 1 (17-03-2016)

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Pierre Guillot, Pascal Philippe, Corinne Berland, Jean-François Bercher. A 2GHz 65nm CMOS digitally-tuned BAW oscillator. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Aug 2008, St. Julian's, Malta. pp.722-725, ⟨10.1109/ICECS.2008.4674955⟩. ⟨hal-00621923⟩
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