High-throughput block turbo decoding: from full-parallel architecture to FPGA prototyping - Archive ouverte HAL
Article Dans Une Revue Journal of Signal Processing Systems Année : 2009

High-throughput block turbo decoding: from full-parallel architecture to FPGA prototyping

Résumé

Ultra high-speed block turbo decoder architectures meet the demand for even higher data rates and open up new opportunities for the next generations of communication systems such as fiber optic transmissions. This paper presents the implementation, onto an FPGA device of an ultra high throughput block turbo code decoder. An innovative architecture of a block turbo decoder which enables the memory blocks between all half-iterations to be removed is presented. A complexity analysis of the elementary decoder leads to a low complexity decoder architecture for a negligible performance degradation. The resulting turbo decoder is implemented on a Xilinx Virtex II-Pro FPGA in a communication experimental setup which also includes an innovative parallel product encoder. The implemented block turbo decoder processes input data at 600 Mb/s. The component code is an extended Bose, Ray-Chaudhuri, Hocquenghem (eBCH(16,11)) code. Some solutions to reach even higher data rates are finally presented.

Domaines

Electronique
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Dates et versions

hal-00573268 , version 1 (03-03-2011)

Identifiants

Citer

Camille Leroux, Christophe Jego, Patrick Adde, Michel Jezequel. High-throughput block turbo decoding: from full-parallel architecture to FPGA prototyping. Journal of Signal Processing Systems, 2009, 53 (3), pp.349 -- 361. ⟨10.1007/s11265-008-0316-1⟩. ⟨hal-00573268⟩
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