Hierarchical conditional dependency graphs as a unifying design representation in the CODESIS high-level synthesis system
Résumé
In high-level hardware synthesis (HLS), there is a gap in the quality of the synthesized results between data-flow and control-flow dominated behavioral descriptions. Heuristics destined for the former usually perform poorly on the latter. To close this gap, the CODESIS interactive HLS tool relies on a unifying intermediate design representation and adapted heuristics that are able to accommodate both types of designs, as well as designs of a mixed data-flow and control-flow nature. Preliminary experimental results in mutual exclusiveness detection and in efficiently scheduling conditional behaviors, are encouraging and prompt for more extensive experimentation.
Mots clés
flow graphs
high level synthesis
interactive systems
scheduling
CODESIS interactive high-level synthesis system
adapted heuristics
conditional behaviour scheduling
control-flow dominated behavioural descriptions
data-flow dominated behavioural descriptions
hierarchical conditional dependency graphs
high-level hardware synthesis
mutual exclusiveness detection
synthesised results quality
unifying intermediate design representation
Domaines
Systèmes embarqués
Origine : Fichiers produits par l'(les) auteur(s)
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