A FPGA-prototype of a sliding-mode-controller IC for high-switching-frequency DC-DC converters
Résumé
A sliding mode control (SMC) algorithm dedicated to switching mode power supply (SMPS) is validated experimentally in a FPGA. A constant high switching frequency is obtained using an hybrid digital pulse width modulator (DPWM). The proposed SMC strategy cooperates with an off-chip ADC and the hybrid DPWM takes advantage of a digital clock manager (DCM) and a counter-comparator based DPWM with a Multi-stAage-noise-SHaping (MASH) ¿-¿ modulator. Experimental results verify closed-loop operation at switching frequency up to 4 MHz only limited by the discrete SMPS and its dynamic response less than 30 ¿s. Simulation results show that the complete digital controller chip in 0.35 ¿m CMOS process takes 0.72 mm2 of silicon area and the current consumption is roughly 100 ¿A/MHz for a dynamic response of 16 ¿s.
Mots clés
sliding-mode-controller
switching mode power supply
¿-¿ modulator
counter-comparator
analog-digital converters
DC-DC converters
variable structure systems
CMOS process
size 0.35 mum
hybrid digital pulse width modulator
digital controller chip
switched mode power supplies
sigma-delta modulation
CMOS integrated circuits
field programmable gate arrays
digital control
DC-DC power convertors
comparators (circuits)
digital clock manager