EMC assessment at chip and PCB level: use of the ICEM model for jitter analysis in an integrated PLL - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue IEEE Transactions on Electromagnetic Compatibility Année : 2007

EMC assessment at chip and PCB level: use of the ICEM model for jitter analysis in an integrated PLL

Mohamed Ramdani
Richard Perdriau
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Dates et versions

hal-00438288 , version 1 (03-12-2009)

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  • HAL Id : hal-00438288 , version 1

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Jean-Luc Levant, Mohamed Ramdani, Richard Perdriau, M'Hamed Drissi. EMC assessment at chip and PCB level: use of the ICEM model for jitter analysis in an integrated PLL. IEEE Transactions on Electromagnetic Compatibility, 2007, 49, pp.182-191. ⟨hal-00438288⟩
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