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Preprints, Working Papers, ... Year : 2007

More Instruction Level Parallelism Explains the Actual Efficiency of Compensated Algorithms

Abstract

The compensated Horner algorithm and the Horner algorithm with double-double arithmetic improve the accuracy of polynomial evaluation in IEEE-754 floating point arithmetic. Both yield a polynomial evaluation as accurate as if it was computed with the classic Horner algorithm in twice the working precision. Both algorithms also share the same low-level computation of the floating point rounding errors and cost a similar number of floating point operations. We report numerical experiments to exhibit that the compensated algorithm runs at least twice as fast as the double-double one on modern processors. We propose to explain such efficiency by identifying more instruction level parallelism in the compensated implementation. Such property also applies to other compensated algorithms for summation, dot product and triangular linear system solving. More generally this paper illustrates how this kind of performance analysis may be useful to highlight the actual efficiency of numerical algorithms.
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Dates and versions

hal-00165020 , version 1 (24-07-2007)

Identifiers

  • HAL Id : hal-00165020 , version 1

Cite

Philippe Langlois, Nicolas Louvet. More Instruction Level Parallelism Explains the Actual Efficiency of Compensated Algorithms. 2007. ⟨hal-00165020⟩

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